CHIPS Act and Global Semiconductor Reshoring: A Mid-2026 Progress Report for Procurement Leaders

Table of Contents

• CHIPS Act Logic Fab Progress: Project-by-Project Status
• In Production
• Under Construction (Production Start 2026-2027)
• Key Observation: The 2026-2027 Capacity Inflection
• The Cost Question: Why Reshored Wafers Are More Expensive
• Beyond the United States: Global Reshoring Update
• Japan: The Most Aggressive Incentives Program (Per Capita)
• European Union: The European Chips Act
• India and Southeast Asia
• The Procurement Scorecard: What All This Means for Component Buyers
• References and Further Reading

In April 2026, the U.S. Department of Commerce announced the final round of CHIPS Act awards under its original $39 billion manufacturing incentives program: $1.6 billion to Texas Instruments for its Sherman, Texas and Lehi, Utah 300mm fabs; $1.2 billion to SK Hynix for its West Lafayette, Indiana HBM advanced packaging facility; and $800 million to GlobalFoundries for its Malta, New York expansion and a new Vermont Gallium Nitride (GaN) fab.

With those announcements, the CHIPS Program Office has now allocated $38.7 billion of the $39 billion fund across 23 recipients. Approximately $11 billion has been physically disbursed—paid out against verified construction and equipment milestones. The remaining committed funds will disburse through 2028 as projects reach their negotiated milestones.

Three and a half years after the CHIPS and Science Act was signed into law (August 2022), the question for electronics procurement professionals is no longer “Will this actually happen?” It is “What does reshored semiconductor capacity mean for my component availability, pricing, and sourcing strategy—and on what timeline?”

This article provides a current, project-by-project assessment of major CHIPS Act-funded fab construction progress, the capacity volumes and process nodes coming online, and the procurement implications that matter for component buyers.

CHIPS Act Logic Fab Progress: Project-by-Project Status

In Production

TSMC Arizona Fab 21 Phase 1 (Phoenix, AZ)

• Process: 4nm (N4) FinFET
• Capacity: 24,000 wpm (300mm wafer starts per month)
• CHIPS Act funding: $6.6 billion (grant + investment tax credit)
• Status: Volume production began Q1 2026. Apple, AMD, and NVIDIA are confirmed as initial customers.
• Procurement significance: This is the most advanced logic process node currently in volume manufacturing on U.S. soil. The 24,000 wpm capacity represents roughly 2% of TSMC’s global wafer capacity but approximately 8-10% of TSMC’s 4nm capacity. For fabless chip companies designing on TSMC N4, Arizona provides a “Made in USA” wafer source—important for defense, aerospace, and certain government procurement programs with domestic manufacturing requirements.

Intel Ohio Module 1 (New Albany, OH)

• Process: 18A (1.8nm-class) RibbonFET + PowerVia
• Capacity: 30,000 wpm (initial ramp)
• CHIPS Act funding: $8.5 billion (largest single CHIPS award)
• Status: Volume production began Q4 2025. Intel is manufacturing its own products (Panther Lake client CPU, Clearwater Forest server CPU) plus foundry customers including Amazon (Trainium 3 AI accelerator) and Microsoft.
• Procurement significance: Intel 18A is a genuinely competitive leading-edge process. For procurement teams at fabless semiconductor companies, Intel Foundry represents a potential second source to TSMC at the leading edge—something that did not exist a decade ago. However, Intel Foundry’s external customer volume remains small relative to TSMC, and multi-year capacity commitments are required for meaningful wafer allocation.

Samsung Taylor Fab 1 (Taylor, TX)

• Process: 3nm GAA (SF3)
• Capacity: 15,000 wpm (initial ramp)
• CHIPS Act funding: $6.4 billion
• Status: Ramp began late 2025. Samsung LSI (internal) is the anchor tenant, plus foundry customers for mobile SoC and HPC applications.
• Procurement significance: Samsung SF3 is the only GAA (Gate-All-Around) transistor architecture in volume production globally, offering a technology differentiation from TSMC FinFET. For procurement teams, Samsung represents a third-source option at the leading edge alongside TSMC and Intel.

Under Construction (Production Start 2026-2027)

Project	Process	Planned Capacity	CHIPS Award	Production Target	Status
TSMC Arizona Fab 21 Phase 2	3nm (N3)	24,000 wpm	Included in $6.6B	H2 2027	Shell complete; equipment installation begins Q3 2026
TSMC Arizona Fab 21 Phase 3	2nm (N2) or A14	24,000 wpm	Included in $6.6B	2029-2030	Under construction; shell expected complete H1 2027
Intel Ohio Module 2	18A → 14A	30,000 wpm	Included in $8.5B	H2 2027	Shell complete; equipment being installed
Samsung Taylor Fab 2	2nm GAA	20,000 wpm	Included in $6.4B	2028	Under construction
Texas Instruments Sherman Fab 1 (RFAB3)	28nm-130nm	50,000 wpm	$1.6B	H2 2026	Near complete; equipment installation underway
Texas Instruments Lehi LFAB2	28nm-130nm	40,000 wpm	$1.6B (combined with Sherman)	Q1 2027	Equipment installation
Micron Boise Fab 1	DRAM (1β/1γ)	50,000 wpm	$6.1B	2027	Under construction
Micron Clay, NY Fab 1	DRAM (1γ/1δ)	50,000 wpm	Included in $6.1B	2028-2029	Site preparation; construction start H2 2026
SK Hynix West Lafayette	HBM Advanced Packaging	N/A (packaging)	$1.2B	2028	Site preparation

Key Observation: The 2026-2027 Capacity Inflection

The three fabs currently in volume production have a combined capacity of approximately 69,000 wpm. The fabs currently under construction with 2026-2027 start dates represent an additional ~175,000 wpm of U.S.-based advanced and mature logic capacity, plus the DRAM and packaging projects. By the end of 2028, U.S.-based semiconductor manufacturing capacity will have roughly tripled from the 2025 level.

For procurement, the practical implication is that the U.S. capacity buildout is real and measurable—but it is a 2027-2029 story for most component categories. Components procured in 2026 are overwhelmingly manufactured on pre-CHIPS Act capacity in Taiwan, Korea, Japan, and China. The reshoring benefit for procurement is concentrated in the 2028-2032 timeframe, when the capacity under construction today reaches mature yields.

The Cost Question: Why Reshored Wafers Are More Expensive

The CHIPS Act was successful in attracting capital investment to the United States. It has been less successful—and, in fairness, was not designed—to make U.S.-based semiconductor manufacturing cost-competitive with Asia-based manufacturing. The cost gap between U.S. and Taiwan wafer production is approximately 20-30% for equivalent process nodes, and industry analysis suggests this is structural rather than transitional.

Construction Cost Gap. Semiconductor fabrication facilities in the United States cost approximately 2-4x more to build than equivalent facilities in Taiwan or Korea, per industry construction cost benchmarks. The TSMC Arizona fab construction budget was estimated at $12 billion for Phase 1 alone (24,000 wpm), compared to approximately $5-7 billion for an equivalent-capacity fab in Taiwan. The cost differential is driven by higher U.S. construction labor costs, more stringent permitting and environmental review requirements, and the absence of the clustered construction expertise and equipment supply chain that exists in Taiwan’s science parks.

Operating Cost Gap. Once built, U.S.-based fabs cost approximately 30-40% more to operate than equivalent Taiwan-based fabs. Higher U.S. technician and engineer salaries account for roughly half the gap. Higher costs for ultrapure water, bulk gases, chemicals, and other fab consumables—many of which are manufactured in Asia and must be shipped to U.S. fabs—account for most of the remainder. Taiwan’s Hsinchu Science Park, where TSMC’s most advanced fabs are concentrated, benefits from an ecosystem of suppliers, utilities, and logistics infrastructure that has been optimized for semiconductor manufacturing over four decades.

The CHIPS Act Partially Offsets—But Does Not Close—The Gap. The Investment Tax Credit (ITC) of 25% on semiconductor manufacturing equipment and facility construction, combined with the direct grant funding, reduces the effective capital cost of U.S. fab construction by approximately 30-40%. This explains why the projects are happening—the CHIPS Act incentives make the investment economics viable. But the ITC and grants do not address the ongoing operating cost disadvantage, which flows through to wafer pricing.

For procurement teams, the implication is clear: do not expect reshored U.S. semiconductor manufacturing to deliver cost savings on component pricing. The value proposition of U.S.-based manufacturing is supply chain diversification, reduced geopolitical concentration risk, and domestic manufacturing requirements compliance—not lower unit costs. The most cost-competitive manufacturing will continue to be in Asia for the foreseeable future, China in particular for mature-node and commodity products.

Beyond the United States: Global Reshoring Update

The semiconductor manufacturing capacity buildout is global, not U.S.-only. Every major semiconductor-consuming region has deployed some form of incentives program to attract or retain manufacturing:

Japan: The Most Aggressive Incentives Program (Per Capita)

Japan has committed approximately ¥4 trillion ($26 billion) in semiconductor manufacturing subsidies, targeting both logic and memory:

• Rapidus 2nm Foundry (Chitose, Hokkaido): ¥920 billion in government support. IBM 2nm technology transfer. Risk production scheduled for 2027; volume H2 2027. A deeply ambitious project—Rapidus is a startup foundry targeting the most advanced node in the world. Industry skepticism about execution timeline is significant.
• TSMC Kumamoto (JASM) Fab 1: 28/22nm and 12/16nm, 55,000 wpm. In volume production since Q4 2024. Fab 2 (6/7nm, 2027 start) construction underway. The Japanese government is covering roughly 40% of JASM’s capital cost.
• Kioxia/Western Digital Yokkaichi and Kitakami: 3D NAND capacity expansions with ¥240 billion in government support.

European Union: The European Chips Act

The EU Chips Act, passed in 2023, targets €43 billion in public and private investment to double Europe’s global semiconductor manufacturing share to 20% by 2030:

• TSMC ESMC Dresden (Germany): 28/22nm and 16/12nm, 40,000 wpm. Joint venture with Bosch, Infineon, and NXP. Construction began Q3 2024; production start H2 2027. €5 billion EU/German government support.
• Intel Magdeburg (Germany): Originally planned as 18A/14A leading-edge logic with €10 billion in German government support. Construction start has been delayed multiple times; current status uncertain as Intel’s financial difficulties (2025 workforce reduction of 15,000, $10 billion cost-reduction program) have raised questions about the Magdeburg project timeline.
• STMicroelectronics Crolles (France): 18nm FD-SOI and legacy node expansion. €2.9 billion in French government support. On track for 2027 production.

India and Southeast Asia

• Micron Sanand (Gujarat, India): ATMP (Assembly, Test, Marking, Packaging) facility. $2.75 billion investment with Indian government support. Production began 2025. This is a packaging and test facility, not a wafer fab—India’s semiconductor manufacturing strategy starts with the back end.
• Tata/PSMC Fab (Dholera, India): 28nm and legacy nodes. Joint venture with Taiwan’s PSMC. Construction began 2025; production target 2027-2028.
• Malaysia and Vietnam: Both countries are attracting substantial OSAT and packaging investment, positioning themselves as alternatives to China for backend manufacturing.

The Procurement Scorecard: What All This Means for Component Buyers

The global semiconductor reshoring investment amounts to roughly $400-500 billion cumulatively across the U.S., EU, Japan, Korea, China, and India over the 2022-2030 period, when private investment catalyzed by government incentives is included. That is a generational reconfiguration of the industry’s manufacturing footprint.

For procurement professionals buying electronic components, the implications are:

Near-Term (2026-2027): Minimal Change. The fabs currently in production represent a small fraction of global capacity. Most components procured in this period will continue to be manufactured in Taiwan, Korea, and China, with the same lead time, pricing, and allocation dynamics that have prevailed since the post-pandemic recovery. Continue to execute standard supply assurance strategies: dual sourcing where feasible, safety stock on long-lead-time items, and ongoing BOM risk monitoring.

Medium-Term (2028-2030): Geographic Diversification Becomes Real. When the fabs currently under construction reach mature volume production, the geographic concentration of semiconductor manufacturing will have meaningfully decreased. For advanced logic, the U.S., Taiwan, Korea, and Japan will all have competitive manufacturing capability. This reduces the systemic risk of a single-region disruption (earthquake, geopolitical event, etc.) affecting the entire global supply of advanced semiconductors.

Long-Term (2030+): The China Factor. China’s semiconductor manufacturing investment, while largely excluded from advanced logic by U.S. export controls on EUV equipment, is building enormous mature-node capacity. China now accounts for an estimated 30%+ of global 28nm-and-above capacity, and this share continues to grow. For procurement teams buying mature-node components—analog ICs, MCUs, discretes, basic logic—Chinese manufacturing will be an increasingly unavoidable part of the supply base. Understanding the quality, traceability, and export control compliance implications of the China-based supply chain is not optional.

Cost: Higher, Not Lower. The reshoring buildout is adding structural cost to the semiconductor supply chain. Higher-construction-cost fabs with higher operating costs produce more expensive wafers. The CHIPS Act incentives make the projects viable for the companies building them, but do not pass through to lower component pricing for the companies buying the output. Procurement budgets should model flat to slightly increasing component costs in real terms over the medium term.

The Trust Premium. For applications with domestic manufacturing requirements (defense, aerospace, certain government programs, some critical infrastructure), the availability of advanced U.S.-based semiconductor manufacturing is a genuine improvement in supply assurance. Components manufactured on U.S.-based fabs can meet domestic sourcing requirements that were impossible to fulfill when advanced logic was manufactured exclusively in Taiwan and Korea.

References and Further Reading

• NIST CHIPS Program Office: Official CHIPS Act award announcements, milestone disclosures, and program updates
• SIA — Semiconductor Industry Association: U.S. semiconductor manufacturing capacity data, CHIPS Act impact analysis, and industry statistics
• TSMC — Investor Relations: Arizona fab progress, capacity allocation updates, and global fab construction timelines
• Intel — Investor Relations: Ohio fab progress, 18A/14A technology milestones, and Intel Foundry customer disclosures
• Samsung Semiconductor — Newsroom: Taylor fab construction progress and SF3 GAA technology updates
• Micron Technology — Investor Relations: Boise and Clay, New York DRAM fab construction status
• SK Hynix — Newsroom: West Lafayette HBM packaging facility progress
• European Commission — EU Chips Act: EU semiconductor manufacturing incentives and project disclosures
• Japan METI — Semiconductor Strategy: Rapidus, JASM, and Japanese semiconductor manufacturing incentives