Table of Contents
A supply offer for XC2C128-7VQG100I solves only part of a maintenance problem. The delivered CPLD must also accept the approved programming image and reproduce the timing and startup behavior of the released board. A physically compatible package without a recoverable programming flow can leave a repair program blocked.
This guide addresses continuity for an existing design. It combines AMD’s published discontinuation notice with a buyer-and-engineer release checklist; it does not establish current stock or approve a replacement.
Discontinuation dates and the remaining supply question
AMD’s XCN23009, revision 1.1, dated January 29, 2024, includes CoolRunner II and identifies the XC2C128-VQG100 package variant among affected products. Its stated final-order date was June 29, 2024, and final deliveries were due by December 28, 2024. The notice lists no direct replacement for this variant.
Those dates were checked on September 15, 2026. A present-day seller offer therefore needs its own explanation of material origin and custody. The existence of residual inventory does not reopen the manufacturer’s historical order window.
The XC2C128-7VQG100I catalog entry can identify the sourcing request, but a catalog listing is not a lot reservation. Obtain quantity, location, lot photographs, packing condition, and a written delivery proposal for the actual material.
Ordering-code constraints
The XC2C128 specification, DS093, describes a 128-macrocell device with a nominal 1.8 V core supply and separate I/O supply requirements. Its 100-pin VQFP option exposes 80 user I/Os; other packages do not have the same pin arrangement.
| Code element | What to verify | Consequence of a mismatch |
|---|---|---|
| XC2C128 | Device family and density | A similar name is not proof of the same implementation |
| -7 | Speed grade against the released timing report | A different grade requires timing review |
| VQG100 | Exact package, lead finish, drawing, and board footprint | A 100-pin label alone is insufficient |
| I | Industrial grade and applicable electrical tables | Commercial-grade limits cannot replace industrial requirements by assumption |
Treat a faster speed grade as a candidate deviation, too. Minimum delays, clock relationships, and external timing still matter. Let engineering record the accepted difference rather than shortening the purchase description to “XC2C128 equivalent.”
The programming continuity package
Create a continuity package containing the approved JEDEC programming file, its hash, source project where available, fitter and timing reports, pin assignments, tool version, programmer model, cable configuration, and board-level test procedure.
Run that flow on a known-good board before evaluating incoming samples. This separates a failing programmer, missing license, incorrect power rail, or unavailable build environment from a material problem. Where only the final image survives, record that the design can be programmed but may not be reproducibly rebuilt.
Security settings may limit readback. Establish how programming is verified using the supported device procedure and a functional test, without depending on extracting firmware from an unknown unit. Confirm the delivered state: blank, previously programmed, or programmed to an agreed customer image.
Material acceptance and design acceptance
Commercial acceptance and design acceptance need different records.
The material record should connect the seller’s shipment to identifiable lots, condition, original or replacement packing, inspection results, and agreed remedies. The design record should show successful programming and operation on representative hardware, including power cycling, reset, I/O states, and timing-sensitive functions.
Neither record substitutes for the other. Passing a simple board test does not reconstruct missing traceability; complete paperwork does not demonstrate that the archived programming image still works. Use the broader obsolete-component quote verification process to define unresolved material questions.
Bridge stock with a defined exit
A bridge order should cover a named service or production interval while engineering evaluates a successor. Include units consumed by programming qualification, destructive inspection if required, assembly loss, and repair demand. Keep those quantities separate so they can be revised independently.
For a migration through the component alternatives workflow, begin with the logic function, interfaces, and timing constraints. A new programmable device may require a different supply, footprint, programmer, or HDL implementation even when it has more resources.
The useful exit condition is a validated replacement board and a service plan for the installed base. “A larger CPLD has been found” is only the start of that work.
Frequently Asked Questions (FAQ)
Can another 128-macrocell CPLD replace XC2C128-7VQG100I?
Macrocell count alone does not establish compatibility. Compare package pins, supply rails, I/O behavior, timing constraints, programming flow, and the implemented logic. A different family normally requires a design migration and board-level validation.
Does a readable JTAG ID prove that a CPLD is authentic?
No. A device identifier is one consistency check. It does not establish source history, previous use, correct speed grade, or complete electrical performance.
Should a buyer accept a programmed part?
Only when the required programming state and verification procedure are explicitly agreed. Preserve the approved image and test records; do not assume an unknown programmed device can be read back or reused.
